MOSFET amplifier

Assume in the circuit above $V_{in}=V_{GS}>V_T$ and the transistor is in saturation region, i.e., $V_{DS}>V_{in}-V_T$, then we have

$$\left\{ \begin{array}{l} I_{DS}=K(V_{in}-V_T)^2 \\ V_{out}=V_{DS}=V_{dd}-I_{DS} R=V_{dd}-KR(V_{in}-V_T)^2 \end{array} \right.$$

The second equation relates the output $V_{out}$ to the input $V_{in}$, as shown by the red segment of the curve in the plot above. As the transistor is in saturation region,

$$V_{out}=V_{dd}-KR(V_{in}-V_T)^2\ge V_{in}-V_T$$

which can be solved for $V_{in}$ to get:

$$V_{in}<\frac{-1+\sqrt{1+4KRV_{dd}}}{2KR}+V_T$$

It can be seen that when the transistor is in saturation mode the slope of the curve (red) indicates the ratio between input $V_{in}$ and output $V_{out}$. And the voltage gain of the circuit is defined as:

$$g=\frac{d V_{out}}{d V_{in}}=\frac{d}{d V_{in}}(V_{dd}-K(V_{in}-V_T)^2 R) =-2KR(V_{in}-V_T)$$

Example: Assume $V_{dd}=10V$, $R=10 k\Omega$, $K=0.5\;mA/V^2$, $V_T=1V$. For the transistor to be in saturation region, we need

• $V_{in}>V_T=1\;V$
• $V_{in}<[-1+\sqrt{1+4KRV_{dd}}\;]/2KR+V_T=2.32\;V$

then we have

$$V_{out}=V_{dd}-K(V_{in}-V_T)^2 R=10-5(V_{in}-1)^2$$

and the voltage gain is a function of the input $V_{in}$:

$$g(V_{in})=\frac{d}{d V_{in}} V_{out}(V_{in})=-10(V_{in}-1)$$

This nonlinear equation can be represented by the table below:

$V_{in}$	0	1	1.4	1.5	1.8	1.9	2.0	2.1	2.2	2.3	2.32	2.35	2.4
$V_{out}$	10	10	9.2	8.8	6.8	6.0	5.0	4.0	2.8	1.6	1.3	0.9	0.0

In particular, when the input $V_{in}$ increases from $1.8V$ to $1.9V$, the output $V_{out}$ decreases from $6.8V$ to $6V$, with a gain $g(V_{in})=g(1.8)=-10(1.8-1)=-8$. Also when the input $V_{in}$ increases from $2.0V$ to $2.1V$, the output $V_{out}$ decreases from $5V$ to $4V$, with a gain $g(V_{in})=g(2)=-10(2-1)=-10$.

In summary, we see that

• When the transistor is in saturation mode, the circuit behaves as a voltage amplifier.
• The voltage gain is the slope of the tangent of the curve (red) as a function of $V_{in}$.
• The value of the gain depends on the level of input $V_{in}$. When $V_T=1V<V_{in}<2.32V$, the gain $\vert g\vert>1$ is greater than one.
• The output voltage is $180^\circ$ out of phase with the input voltage ($g<0$), as the slope of $V_{out}(V_{in})$ is negative.
• When $V_{in}<V_T=1V$, the transistor is cutoff. On the other hand, when $V_{in}>2.32V$, $V_{out}$ is more than one $V_T$ below $V_{in}$, for example, $V_{in}=2.32$, $V_{out}=1.3<V_{in}-V_T=2.32-1=1.32$, the transistor is in triode region. In either of the two cases, the transistor has no amplification capability.

Next we consider a MOSFED circuit with sinusoidal input. Assume the drain resistor is $R=10\;k\Omega$, $K=1\;mA/V^2$, $V_T=1V$, $V_{dd}=5V$ and a sinusoidal input $v_{in}(t)=V_{bias}+\sin(\omega t)$. If the bias voltage is $V_{bias}=1.5V$, the input voltage $v_{in}(t)$ varies between 1.4V and 1.6V. The output voltage can be found to be:

$$v_{out}=V_{dd}-RI_{DS}=V_{dd}-RK(V_{in}-V_T)^2=5-10 (V_{in}-1)^2$$

In particular, corresponding to $V_{in}=1.4V,\;1.5V,\;1.6V$, the output voltage $v_{out}$ and the current $i_{DS}$ are, respectively, $v_{out}=3.4V,\;2.5V,\;1.4V$, and $i_{DS}=0.16mA,\;0.25mA,\;0.36mA$, as shown in the figure below:

Biasing: In the example above, the DC offset of the input is at 1.5V, so that the transistor is working in the saturation region when the magnitude of the AC input is limited. However, if this offset is either too high or too low, the gate voltage may go beyond the saturation region to enter either the triode or the cutoff region. In either case, the output voltage will be severely distorted, as shown below:

It is therefore clear that the DC offset or biasing gate voltage has to be properly setup to make sure the dynamic range of the input signal is within the saturation region.

Method 1: One way to provide the desired DC offset is to use two resistors $R_1$ and $R_2$ that form a voltage divider, as shown in the figure below (a). As the input resistance of a MOSFET transistor is very high, therefore the gate of the transistor does not draw any current, the DC offset voltage can simply obtained as:

$$V_{bias}=V_{dd}\frac{R_1}{R_1+R_2}$$

The input AC signal through the input capacitor is then superimposed on this DC offset.

Method 2: Another way to set up the bias is the circuit shown in (b) above. Assume $R_1=84k$, $R_2=16k$, $R_d=20k$, $V_{dd}=10V$, and $K=0.5mA/V^2$. The bias voltage can be found to be $V_B=V_{bias}=1.6V$, and the voltage between gate and source is $V_{GS}=V_B-V_{in}$. The output voltage is

$$V_{out}=V_{dd}-R_d K (V_{GS}-V_T)^2=V_{dd}-R_d K (V_B-V_{in}-V_T)^2=10-10\times (0.6-V_{in})^2$$

When $V_{in}=0$, $V_{out}=6.4V$.

To determine the dynamic range of the input $V_{in}$, recall the conditions for the transistor to be in saturation region:

• To avoid cutoff region: $V_{GS}-V_T \ge 0$. For this particular circuit,
  
  $$V_{GS}-V_T=V_B-V_{in}-V_T=0.6-V_{in} \ge 0$$
  
  
  Solving this we get $V_{in} \le 0.6V$ with corresponding output $V_{out} < 10V$.

• To avoid triode region: $V_{DS} \ge V_{GS}-V_T$. For this particular circuit,
  
  $$V_{DS}=V_{out}-V_{in}=(V_{dd}-R_dI_{DS})-V_{in} =V_{dd}-R_dK (V_B-V_{in}-V_T)^2-V_{in} \ge V_B-V_{in}-V_T$$
  
  
  that is
  
  $$V_{out}=V_{dd}-R_dK (V_B-V_{in}-V_T)^2 \ge V_B-V_T$$
  
  
  i.e.,
  
  $$V_{out}=10-10\times (0.6-V_{in})^2 \ge 0.6$$
  
  
  Solving this for $V_{in}$ we get $V_{in} \ge -0.37V$, with corresponding output $V_{out} \ge 0.6V$

Therefore the overall dynamic range for the input is

$$-0.37V \le V_{in} \le 0.6V$$

with the corresponding output range

$$0.6V \le V_{out} \le 10V$$

and the overall voltage gain is about $g=9.7$. Note that the output voltage is in phase with the input voltage.

Source Follower: If the output is taken from the source, instead of the drain of the transistor, the circuit is called a source follower.

Assume $R_S=10 k\Omega$, $V_T=1V$ and $K=10 mA/V^2$. To find the input and output voltages and the gain of the circuit, consider the current $I_{DS}=V_{out}/R_S$:

$$I_{DS}=K(V_{GS}-V_T)^2=K(V_{in}-V_{out}-V_T)^2=V_{out}/R_S$$

Plugging in the given values, we get

$$(V_{in}-V_{out}-1)^2=V_{out}$$

If $V_{in}=2V$, this equation becomes:

$$(V_{out}-1)^2=V_{out}$$

which can be solved to get $V_{out}=2.6V$ or $V_{out}=0.4V$. We take the smaller voltage in order for the transistor to be outside the cutoff region:

$$V_{GS}=V_{in}-V_{out}=2-V_{out}>V_T=1$$

Similarly, if $V_{in}=3V$, the equation becomes:

$$(V_{out}-2)^2=V_{out}$$

and we get $V_{out}=1V$. The voltage gain of the source follower is

$$g=\frac{\Delta V_{out}}{\Delta V_{in}}=\frac{1-0.4}{3-2}=0.6<1$$