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CMOS Digital Logic Circuits

Either a p-channel MOSFET (pMOS or PFET) or an n-channel MOSFET (nMOS or NFET) can be treated as a switch between its drain $D$ and source $S$ controlled by the voltage $V_{gs}$ between gate $G$ and source $S$. When $V_{gs}>V_{Tn}$ (e.g., $V_{Tn}=1\;V$) for nMOS and $V_{gs}\le V_{Tp}$ (e.g., $V_{Tp}=-1\;V$) for pMOS, the circuit is a short-circuit because of the low resistance between $D$ and $S$; otherwise, the circuit is an open-circuit due to the large resistance between $D$ and $S$. A circuit composed of both types of MOSFET transistors is called a complementary MOS or CMOS circuit, which is widely used in digital systems.

When two switches are connected in series, the resulting circuit conducts only if both switches conduct, i.e., the circuit implements logic AND. On the other hand, when two switches are connected in parallel, the resulting circuit conducts if either of the two switches conducts, i.e., the circuit implements logic OR.

Due to such logic properties of the series and parallel connections of the pMOS and nMOS transistors, various logic circuits can be constructed to realize a given logic function $f(a,b,\cdots,x)$, where each of the inputs $a,b,\cdots,x$ is either a low or high a voltage, representing, respectively, logic value 0 or 1. Corresponding to each possible combination of the inputs, the output is either low or high in voltage for logic 0 or 1.

In general, a logic function $f(a,b,\cdots,x)$ is realized by two complementary circuits, one pull-up circuit connected to the voltage source $V_s$, and a pull-down circuit connected to ground, as shown in the figure:

CMOSlogic.gif

When the input variables $a,b,\cdots,x$ are such that the pull-up circuit is conducting (short-circuit) and the complementary pull-down circuit is cutoff (open-circuit), the output $f$ is connected to the voltage source to output a high voltage representing logic 1; however, when the input variables $a,b,\cdots,x$ are such that the pull-up circuit is cutoff (open) and the complementary pull-down circuit is conducting (short), the output $f$ is connected to ground to output a low voltage representing logic 0.

Before discussing the implementation of the pull-up and pull-down circuits, recall the famous De Morgan's Law:

\begin{displaymath}(A+B+C)'=A'\cdot B'\cdot C',\;\;\;\;\;\;\;\;(A\cdot B\cdot C)'=A'+B'+C' \end{displaymath}

Here $A'$ is the negation of variable $A$. In general, the De Morgan's law states that the negation (complementary) of a given function can be found by negating the logical operations (turn AND to OR and OR to AND) as well as the variables in a function.

As the simplest example, the NOT gate is implemented by a pull-up circuit composed of only a pMOS transistor and its complementary pull-down circuit composed of only a nMOS transistor, as shown below:

CMOSnot.gif


\begin{displaymath}\begin{tabular}{cc\vert\vert c\vert c\vert c\vert c}  \hlin...
...& 1 & 1 & 0 \\
1 & 1 & 1 & 1 & 0 & 0  \hline
\end{tabular} \end{displaymath}

CMOSnandnor.gif

More complicated logic functions can be similarly implemented using CMOS circuits.

Example: Implement logic function $f(a,b,c)=(a'+b')c$ by a CMOS circuit.

First, find the complementary function $f'(a,b,c)$:

\begin{displaymath}f'(a,b,c)=(a'+b')'+c'=ab+c' \end{displaymath}

and then the CMOS circuit can be designed as shown: CMOSlogicexample.gif


next up previous
Next: About this document ... Up: ch4 Previous: MOSFET Amplifier
Ruye Wang 2014-07-23