To simplify the analysis of the Op-Amp circuits, we further make the following assumptions:
Current into the op-amp is negligible, and
. Applying KCL to the
node of
, we have
In general,
and
in the inverter can be replaced by two networks
(with impedances
and
respectively) containing resistors and capacitors
and the analysis of the circuit can be carried out easily in frequency domain:
Apply KCL to
:
Define
, we get:
Consider some special cases:
Note 1: It is likely that both inputs are subjected to some common noise
(such as interference of 60Hz power supply):
Note 2: If one of the two inputs, e.g.,
is connected to a constant
voltage treated as a reference
, then the differential amplifier
can also be used as a level shifter. As
One drawback of the differential amplifier is that its input impedance
(
) may not be high enough if the output impedance of the previous
stage is not low enough. To overcome this problem, two non-inverters with
high input resistance can be used each for one of the two inputs to the
differential amplifier. The resulting circuit is shown below:
The analysis of this circuit is very simple. As the output impedance of the
non-inverter is low, the three op-amp circuit can be considered as three
independent circuits. The outputs of the two non-inverters are:
Alternatively, we consider the current going from
to
:
Define
. Apply KCL to
and
we get:
Without feedback, the output of an op-amp is
. As
is
large,
is saturated, equal to either the positive or the negative
voltage supply, depending on whether or not
is greater than
.
These two possible outputs, positive and negative, can be treated as ``1''
and ``0'' of the binary system. The figure shows an A/D converter built by
three op-amps to measure voltage
from 0 to 3 volts with resolution 1 V.
Due to the voltage divider, the input voltages to the three op-amps are, respectively, 2.5V, 1.5V and 0.5V. The output of these op-amps are listed below for each of the input voltage levels. A digital logic circuit is then needed to convert the 3-bit output of the op-amps to the two-bit binary representation.
| Voltage (volts) | 0 | 1 | 2 | 3 |
| Op-amps Outputs | 000 | 001 | 011 | 111 |
| Binary Representation | 00 | 01 | 10 | 11 |
Integrator
In time domain, as
and
, we have (KCL)
Differentiator
If we swap the resistor and the capacitor, we get in time domain:
Low-pass filter:
For example, when
,
, the Bode plots are
shown below:
High-pass filter:
For example, when
,
, the Bode plots are
shown below:
Band-pass filter:
For example, when
,
,
, the Bode
plots are shown below:
Higher than first order systems can be built with multiple integrators, as shown here for a third order system:
From the diagram, we can get
From the diagram, we can get
The Sallen–Key topology is an electronic filter topology used to implement second-order active filters that is particularly valued for its simplicity.
We represent the input and output in s-domain as
and
, respectively,
and the voltage at node a as
, and apply KCL to nodes a and b to get:
Example 1
,
,
,
, then we get a second order
low-pass filter:
![]() |
|||
![]() |
Example 2
,
,
,
, then we get a second order
high-pass filter:
![]() |
|||
![]() |