Microprogrammed Control

The control signals needed in each step of intruction execution can be generated by the finite state machine method, also called hardwired control, or, alternatively, by the microprogrammed control method discussed below.

• Basic Concepts of Microprogramming:
  • Control word (CW):

    A word with each bit for one of the control signals. Each step of the instruction execution is represented by a control word with all of the bits corresponding to the control signals needed for the step set to one.

  • Microinstruction:

    Each step in a sequence of steps in the execution of a certain machine instruction is considered as a microinstruction, and it is represented by a control word. All of the bits corresponding to the control signals that need to be asserted in this step are set to 1, and all others are set to 0 (horizontal organization).

  • Microprogram:

    Composed of a sequence of microinstructions corresponding to the sequence of steps in the execution of a given machine instruction.

  • Microprogramming:

    The method of generating the control signals by properly setting the individual bits in a control word of a step.

  $\sim$ $\sim$

  $\sim$ $\sim$ $\sim$

• The program hierarchy

  
  

  $$\begin{array}{c} assembly \\ program: \end{array} \left\{... ...ht. \\ \cdots & \\ instruction\;n; & \end{array} \right.$$
  
  

  

  

• horizontal vs. vertical

  As the CPU may need hundreds of control signals, the control word will be inevitably long. To reduce the length of the control word, groups of control signals that are mutually exclusive (only one of them need be asserted at a time) can be encoded to form shorter fields. This shorter form of control word is called vertical organization.

  For example, if only 1 of a group of 8 signals is needed at any time, they can be encoded into a field of $log_2 8=3$ bits, instead of 8 bits. The price to pay is the time delay needed for decoding the encoded field.

  

• MIPS $\mu$-Programming - Implementation

  

  • There are 10 $\mu$-instructions (control words) needed, each for one of the 10 states.
  • These 10 control words are stored in a read-only control memory (much smaller and faster than the main memory). The index number of the corresponding state is used as the address of each control word in the memory.
  • Each control word has 18 bits, of which 16 are for the control signals. The bits representing the control signals needed in the corresponding state are set to 1, while others are set to 0.
  • Two additional bits AddrCtl0 and AddrCtl1 are also included in each control word to select one of four ways to find the address of the next $\mu$-instruction. (Refer to the state diagram for the FSM of the control unit.)
    • AddrCtl0, AddrCtl1=00:

      Current machine instruction is complete. Go to the $\mu$-instruction in state 0 to fetch the next machine instruction (e.g., $4\rightarrow 0$, $5\rightarrow 0$, $7\rightarrow 0$, $8\rightarrow 0$, $9\rightarrow 0$).

    • AddrCtl0, AddrCtl1=01:

      This is the first conditional branch (state 1). The next $\mu$-instruction is selected from the four possible $\mu$-instructions corresponding to states 2, 6, 8, and 9, depending on the Op-code of IR. This is implemented by a dispatch table stored in ROM1:
      

      $$\begin{tabular}{l\vert l} \hline \multicolumn{2}{c}{Dispatch... ...8) \hline 000010 (jmp) & 1001 (9) \hline \end{tabular}$$
      
      

    • AddrCtl0, AddrCtl1=10:

      This is the second conditional branch (state 2). The next $\mu$-instruction is selected from the two possible $\mu$-instructions corresponding to states 3, and 5, depending on the Op-code of IR. This is implemented by another dispatch table stored in ROM2:
      

      $$\begin{tabular}{l\vert l} \hline \multicolumn{2}{c}{Dispatch... ...(3) \hline 101011 (sw) & 0101 (5) \hline \end{tabular}$$
      
      

    • AddrCtl0, AddrCtl1=11:

      The next $\mu$-instruction is the one that follows the the current one sequentially (e.g., $0\rightarrow 1$, $3\rightarrow 4$, $6\rightarrow 7$).

  The control memory is shown below. Note the state number is used as the address of the corresponding control word.

  
  

  $$\begin{tabular}{c\vert c\vert\vert c\vert c} \hline State & ... ...0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 & 0 0 \hline \end{tabular}$$
  
  

• MIPS $\mu$-Programming - Encoding

  The control words are divided into 8 fields, each representing a set of mutually exclusive operations:

  1. ALU control:

     Tow bits, ALUOp0 and ALUOp1 to specify one of 3 ALU operations:

     • ALUOp0, ALUOp1=00: addition;
     • ALUOp0, ALUOp1=01: subtraction;
     • ALUOp0, ALUOp1=10: operation determined by funct field of IR.

  2. SRC1:

     One bit ALUSrcA to select one of 2 sources of 1st ALU operand:

     • ALUSrcA=0: PC is the 1st ALU operand;
     • ALUSrcA=1: a register is the 1st ALU operand.
  3. SRC2:

     Two bits ALUSrcB0 and ALUSrcB1 to select one of 4 sources of 2nd ALU operand:

     • ALUSrcB0, ALUSrcB1=00: Register $rt;
     • ALUSrcB0, ALUSrcB1=01: constant 4;
     • ALUSrcB0, ALUSrcB1=10: sing-extend(IR(15-0));
     • ALUSrcB0, ALUSrcB1=11: sign_extend(IR(15-0)) $\ll$ 2.
  4. AUL destination:

     specify destination of ALU result;

  5. Memory:

     specify MM operation (read/write) and source of address;

  6. Memory register:

     specify destination for MM read or source for MM write;

  7. PCWrite:

     specify the source for PC write;

  8. Sequencing:

     Two bits AddrCtl0 and AddrCtl1 to select one of 4 ways for finding next $\mu$-instruction (same as above).

  Since mutually exclusive control signals are encoded into fields, fewer bits are needed in the control word than the horizontal organization. But a decoder is needed for each field which costs additional time delay.