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Multiplexer (MUX)

An MUX has N inputs and one output. Under the control of $n=log_2 N$ selection signals, one of the inputs is passed on to the output.

MUX0.png

First consider the truth table of a 2x1 MUX with three inputs $x_0$, $x_1$ and $s$ and only one output $y$:

\begin{displaymath}
\begin{tabular}{r\vert ccc\vert c} \hline
& s & $x_1$ & $x...
...6 & 1 & 1 & 0 & 1 \\
7 & 1 & 1 & 1 & 1  \hline
\end{tabular}\end{displaymath}

2x1_mux_kmap.gif

This truth table can be simplified by allowing Don't-cares in the table:

\begin{displaymath}
\begin{tabular}{ccc\vert c} \hline
s & $x_1$ & $x_0$ & y ...
...1 \\
1 & 0 & x & 0 \\
1 & 1 & x & 1  \hline
\end{tabular}\end{displaymath}

Finally, if we allow variables in the truth table (variable-entered map VEM), the truth table can be further simplified to be

\begin{displaymath}
\begin{tabular}{c\vert c} \hline
s & y  \hline
0 & $x_0$ \\
1 & $x_1$  \hline
\end{tabular}\end{displaymath}

2x1_mux.gif

MUX.gif

A 4x1 MUX has $N=2^n=4$ inputs $x_0$, $x_1$, $x_2$ and $x_3$, and $n=log_2 4=2$ selections $s_0$ and $s_1$. Its output $y$ is one of the four inputs depending on the selections. The truth table for a 4x1 MUX:

\begin{displaymath}
\begin{tabular}{cc\vert cccc\vert c} \hline
$s_1$ & $s_0$\...
... & x & 0 \\
1 & 1 & 1 & x & x & x & 1  \hline
\end{tabular}\end{displaymath}

This truth table can be simplified by the VEM:


\begin{displaymath}
\begin{tabular}{ll\vert l} \hline
$s_1$ & $s_0$ & y  \hl...
... \\
1 & 0 & $x_2$ \\
1 & 1 & $x_3$  \hline
\end{tabular}\end{displaymath}

We see that each minterm of the two selection bits corresponds to an input:


\begin{displaymath}y=\sum_{i=0}^{2^n-1} m_i x_i
=(s'_1s'_0)x_0+(s'_1s_0)x_1+(s_1s'_0)x_2+(s_1s_0)x_3 \end{displaymath}

where $m_i$ is the ith minterm of $\{s_1,s_0\}$.

4x1_mux.gif

This approach can be generalized to any MUX of $2^n$ inputs with $n$ selections.

Note: The AND gates used here can be conceptively considered as guarded gates. To see this, consider an AND function $y=g_1g_0x$:


\begin{displaymath}
\begin{tabular}{ccc\vert c} \hline
$g_1$ & $g_0$ & x & y \...
...& 0 \\
1 & 1 & 0 & 0 \\
1 & 1 & 1 & 1  \hline
\end{tabular}\end{displaymath}

guarded_gate.gif

Only when both signals $g_1$ and $g_0$ are 1, will the output $y$ be the same as input signal $x$. In other words, only when both ``guards'' $g_1$ and $g_0$ agree, can the signal $x$ go through the gate.


next up previous
Next: MUX for combinational logic Up: Combinational Circuits Previous: Full Adder
Ruye Wang 2014-02-28